This paper presents an active noise-shaping successive-approximation-register analog-to-digital converter. Instead of binary-weighted capacitors, it uses two equal-valued capacitors as a digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is 1, much smaller than that of the conventional binary-weighted capacitor array, and hence the mismatch error can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC's linearity even for a small oversampling ratio (OSR). Also, the proposed architecture uses a monotonic switching procedure which allows fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2kHz bandwidth, it achieved a 78.8 dB SNDR. It consumes 74.2uW power from 1.5V power supply. © 2018 IEEE